CALL FOR PAPERS AND TUTORIALS VHDL International Users Forum Fall 1994 Conference - Sponsored by VHDL International "COMPONENT MODELING" November 13-16, 1994 Ritz Carlton at Tysons Corner Washington, DC The Fall 1994 VIUF Conference builds on the six and a half years of VHDL Users meetings to focus in on Component modeling. Emphasis is made on component models for use in board design and verification. Continuing in the tradition of the Fall meetings this more informal meeting will be based on practical knowledge and user experiences. Component modeling is a critical link in the industrial application of VHDL. The enhanced IEEE VHDL-1993, the industry consensus reached on VITAL, the maturity of VHDL tools and support, and the continual growth in design complexity all contribute to a constantly improving technology base from which designers can draw on to improve their skills. The aim of this meeting is to enable professionals to exchange ideas and gather new information needed to perform and excel in todays challenging world of electronic design. The event will be comprised of paper presentation sessions, panel sessions, tutorials, keynotes, vendor sessions, focus group meetings and exhibits. For the first time, VIUF will be sponsoring a VHDL design contest. See the separate call for participation to obtain more information. TECHNICAL PROGRAM The technical program will consist of technical paper sessions and a few industry expert panel discussions. Papers will be distributed in a bound proceedings at the meeting. Potential authors are encouraged to participate by submitting an abstract and eventually full paper to the Program Chair for consideration. Submissions are especially encouraged in the following focus topic areas: o VITAL based ASIC modeling o Industry standard component modeling o Mixed analog-digital component modeling o Inter-operable VHDL models o Packages/development kits for component modeling o Back annotation techniques o Validation and verification of component models o Test bench development strategies o Design methodology and library development o Modeling for DSP, applications o Critical component modeling styles o Efficient VHDL models o Acceleration of model execution o Designing with component libraries o VHDL 93 specific model features and tools o Performance models, executable specifications o VHDL coding guidelines o RASSP, ECCI and model repository updates TUTORIALS The tutorial program provides in-depth coverage on focused subjects for the attendees. We encourage both beginner, advanced and expert tutorials on subjects related to VHDL and the theme of Component Modeling. Abstracts for tutorials are invited for initial consideration. Authors with accepted abstracts will then be required to submit the full tutorial in advance for content and format screening. The committee is looking first for abstracts in the following areas: o Board Simulation in VHDL o Interoperable (EIA 567) Models o Standard Parts Libraries in VHDL o VITAL and ASIC library modeling o HDL Based Design Methodologies o Using VHDL Development Packages o Testbenches and verifying designs o Performance / Large-system Modeling in VHDL o Synthesis techniques in VHDL o Design management for large VHDL projects SUBMISSIONS AND SCHEDULE INFORMATION Extended abstracts of proposed papers, tutorials, or panel sessions (one page typewritten without drawings) should be sent to the appropriate chair by June 24 1994. Electronic submission of material in RTF, MIF, Postscript, or 7-bit ASCII text is strongly encouraged. Only original papers written in English, which have not been published elsewhere, can be accepted. All material will be reviewed by the appropriate committee. Notification of acceptance will be sent on July 15. An author kit with complete instructions for preparing a camera-ready copy for the proceedings will be sent to accepted authors. All camera-ready copy must be received by August 12, 1994. Note that authors of the technical program will be able to submit their contributions either as a full paper or as a report containing annotated slides. Tutorials are expected in either Note-and-Slide or Slide-only format. Technical program papers, once accepted, become the property of VHDL International. Material sent in cannot be returned. Contact information for each chair is listed on the back. IMPORTANT DATES: Deadline to submit abstract: 24 June 1994 Notification of acceptance: 15 July 1994 Final, camera-ready copy due: 12 August 1994 Presentation of material: 13-16 November 1994 Conference Chair Randolph E. (Randy) Harr Logic Modeling, Synopsys 700C E. Middlefield Road Mountain View, CA 94043 (415) 694-1835 (415) 965-8637 (fax) randyh@vhdl.org Program Chair Alex Zamfirescu Intergraph Electronics 381 East Evelyn Avenue Mountain View, CA 94041 (415) 691-6426 (415) 691-9016 (fax) alexz@vhdl.org TECHNICAL PROGRAM COMMITTEE Doug Perry dougp@redwood.com Victor Berman berman@cadence.com Steve Bailey sbailey@vas.viewlogic.com Andrew Guiler andrew_guiler@ mentorg.com Zain Navabi navabi@nuvlsi.coe.neu.edu Carl Hein chein@atl.ge.com Stan Mazur stan@synopsys.com Stan Krolikosky stank@compass-da.com John Hillawi hillawi@cix.compulink.co.uk Joe Pick jpick@synopsys.com Jean Mermet mermet@imag.fr Jayaram Bhasker jb7@mhcnet.att.com Alex Zamfirescu alexz@vhdl.org Proceedings Chair Carl Hein Martin Marietta Bldg 145-2 Rte 38 Moorestown, NJ 08057-0927 (609) 866-6541 (609) 866-6543 (Fax) Email: chein@atl.ge.com Design Contest Chair Larry Saunders Larry Saunders & Associates 1426 Cedarmeadow Ct San Jose, CA 95131 (408) 894-0119 (408) 894-0119 (fax) lfs@vhdl.org Tutorial Chair Pam Rissmann PROXY Modeling 1580 Washington Blvd. Fremont, CA 94539 (510) 440-8435 (510) 656-2661 (fax) pamr@vhdl.org Exhibit Chair Joe Youmans Bldg. E53, M/S E235 PO Box 902 841 Apollo Street El Segundo, CA 90245 (714) 732-1041 0009227@msgate.emis.hac.com Publicity Chair Nanette Collins Exemplar Logic 2550-9th Street Ste 102 Berkeley, CA 94710 (510) 849-0937 nanette@exemplar.com --------------------------------------------------->% CALL FOR PARTICIPATION VHDL Design Contest VHDL International Users Forum Fall 1994 Conference November 13-16, 1994 Washington, DC There has long been a need for examples of excellent design technique and coding styles in VHDL. To help identify, reward, and proliferate this type of information, the VIUF has embarked on sponsoring a VHDL Design Contest. The contest is being created to help meet this need by encouraging the most accomplished designers to focus their talents on a challenging design problem. The contest winning results will be made available to all as a repository of realistic VHDL models on the VHDL International Internet Services (VIIS) server (vhdl.org). The best designs will be highlighted during the technical program with the winning design announced during the session. CONTEST PROCEDURE The VHDL Design Contest Committee will pose a realistic digital design problem to interested contestants (teams or individuals). The contestants can then employ VHDL and VHDL-based tools to solve the problem. The highest quality results, as judged by our panel of experts, will be made available through the VHDL server. Various criteria including coding style, efficiency, uniqueness and maintainability will be used to judge the submitted designs. The judgment criteria will be made available to contest participants and be detailed during the technical program of the conference. To participate, contestants (teams or individuals) must register by Friday, June 3rd. Send an electronic mail message to viuf94_design_contest@vhdl.org containing the information on the registration form below. If electronic mail is not an option, fax or mail your registration to the Design Contest Chair. Registrations to participate received after June 3rd will only be accepted at the discretion of the conference committee. There is no entry fee to participate in this contest. The contest design problem, supporting information, required submittals and judging criteria will be sent to all registered contestants via mail (electronic, first class, or express post for those outside North America) on Monday, June 13th. All design contest results will be due by Friday, September 2nd. Those selected for presentation will be notified in October. All submissions become the property of VIUF and may be made publicly available on the VIIS machine. Contestants will have to provide a signed copyright release form. The authors of winning entries must agree to participate in a VIUF Design Contest session during the technical program of the conference to make a presentation about their design. There will be a nominal prize awarded to those winners chosen to present. Contest rules are subject to change at anytime at the discretion of the committee. This offer void where prohibited. VHDL Design Contest Registration Form Name (s):___________________________________ Group Name (if applicable):_________________ Title:______________________________________ Affiliation: _______________________________ Street Address:_____________________________ ____________________________________________ City / State / Country: ____________________ ____________________________________________ Phone: _____________________________________ Fax: _______________________________________ Email: _____________________________________ You must register by 3 June 1994 to be eligible for this contest. IMPORTANT DATES: Send registration form by: 3 June 1994 Contest packet sent out: 13 June 1994 Contest results due in: 2 September 1994 Selection for presentation by: 30 September 1994 Presentation of winners: 13-16 November 1994 The Design Contest Committee would like to encourage VHDL tool vendors to sponsor teams and cooperate to enable the best results possible. The vendors of winning teams will be highlighted during the technical session covering the contest results. Conference Chair Randolph E. (Randy) Harr Logic Modeling, Synopsys 700C E. Middlefield Road Mountain View, CA 94043 (415) 694-1835 (415) 965-8637 (fax) randyh@vhdl.org Design Contest Chair Larry Saunders Larry Saunders & Associates 1426 Cedarmeadow Ct San Jose, CA 95131 (408) 894-0119 (408) 894-0119 (fax) lfs@vhdl.org Program Chair Alex Zamfirescu Intergraph Electronics 381 East Evelyn Avenue Mountain View, CA 94041 (415) 691-6426 (415) 691-9016 (fax) alexz@vhdl.org --------------------------------------------------->%