The Rapid prototyping of Application Specific Signal Processors (RASSP) Program

Overview and Status

Information on the Second Annual RASSP Conference is available.

The RASSP Program has established an Education and Facilitation (E&F) effort which serves as the most comprehensive single source of information on the program, its participants, and its status. Click here to explore the RASSP E&F Information Server.

Introduction

The goal of the ARPA/tri-service RASSP program is to dramatically improve the design process for complex digital systems, particularly embedded signal processors. A key objective is to reduce the total product development time by at least a factor of four while making similar improvements in product quality and life cycle cost. Also important will be the ability to field state-of-the-art equipment at system build time and to rapidly upgrade the system throughout its life cycle. RASSP will meet these goals through a combination of advanced design methodology emphasizing virtual prototyping, concurrent engineering, and design re-use; modular, scalable signal processor architectures; and a comprehensive supporting base of electronic design infrastructure, including automation tools, hardware and software libraries, enterprise integration capabilities, and standards. The program has adopted an incremental refinement "model year" design methodology as a way of stressing the importance of continuous improvement, meeting short development schedules (3 to 12 months), and avoiding point design solutions. The model year methodology requires that systems be upgradable on a nominally annual basis, with increasing function and performance. It is expected that most of the results of the RASSP program will be applied to other classes of electronic systems.

The domain of embedded signal processors has been chosen because of its importance to a wide variety of military and commercial applications such as radar imaging, automatic target recognition, and communications. DoD customers will be able to work with the RASSP team to define and carry out demonstration design projects of their own to ensure demonstration relevance and realism and get early customer buy-in. Ongoing RASSP demonstration designs include an infrared search and track image processing module for the AIRMS experimental aircraft, with a model year upgrade to the F-14D; an upgrade to an acoustic sonobuoy coding and communications signal processor; and an architectural tradeoff analysis for a family of classified intelligence signal processors. Additional designs expected to be started soon include a spread spectrum preprocessor for platforms such as JAST, an upgrade to the Navy's UYS-2A standard signal processor for use in the ALFS sonar system, and a new digital front end for the F-15's APG-63 radar.

The RASSP program is also pioneering two innovative concepts for managing a process-oriented program. First, development teams are being benchmarked with semiannual "quizzes"--small design exercises that provide the feedback needed for continuous process improvement. The first two quizzes are based on design of a synthetic aperture radar image formation processor. Second, the program includes an Educator/Facilitator contractor with explicit responsibility to ensure that RASSP design technology transitions effectively to the electronics community at large and continues to mature after completion of the RASSP program.

The new ESTO Program Manager for this effort is:

Last revised 5/12/95