The VHDL Synthesis working group (IEEE 1076.3) is working on standardizing synthesizable VHDL code.

We currently have a preliminary standard, and preliminary versions of the standard VHDL synthesis packages. We have one package which uses "BIT" logic and another which is "STD_LOGIC" (IEEE 1164-1993) based.

• Text version of standard February 13, 1995 version
• Postscript version of standard February 13, 1995 version
• Bit Logic package Rev 2.4
• Std Logic (1164) package Rev 2.4
• Validation and source code for the packages (Yes, we need help here).

The VHDL Synthesis working group has several e-mail aliases on the vhdl.org machine. These are as follows:

vhdlsynth@vhdl.org - Distribution to all VHDLSynth reflector participants.

vhdlsynth-pilot@vhdl.org - "Pilot" team, use to discuss hot topics, limited distribution.

vhdlsynth-request@vhdl.org - Please use this email address for any request to be added/dropped from the reflector list, pilot list, or e-mail problems.

vhdlsynth-info@vhdl.org - Will be responded to by this document.

Other files:

ESA VHDL Modeling Guidelines and activities report.

VHDL random number generator documentation and code.

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Last Updated on 5/1/95